1. Field of the Invention
The invention relates generally to data processing systems and more particularly to the apparatus which receives data type field signals from a descriptor word of an instruction.
2. Description of the Prior Art
Within the data processing industry, there has been continual effort directed to increasing the performance of a computer system while at the same time decreasing the cost of the system. Among the many variables to be considered in an attempt to increase the performance of the data processing system, two very important considerations are the speed of the processor employed within the system and the speed with which data can be transferred between the system memory and the processor unit. One prior art approach to increasing the performance of the data processing system was to provide a plurality of processor units each connected to the system memory over a common data bus. As an extension of this approach, individual processor units were specially designed to execute particular types of processor operations. Thus, the data processing system might include a high speed, scientific processor unit specially adapted to performing complex mathematical calculations at a high level efficiency, a commercial instruction processor specially designed to officially perform operations common in business-related data processing, and a more generalized central processor unit serving as a master processor for controlling the operation of the entire data processing system while also providing additional processing capability.
It was common in such multiple processing data processing systems for each processor to communicate with the system memory by means of individual connections to a common data bus which in turn was connected to the system's memory. The great increase in processing power provided by the use of multiple specially designed processors resulted in a degree of success in increasing the overall performance of the system but the tremendous amount of data constantly being requested by the processors exceeded the capacity of the system's memory to transfer the data to the processors in order to have them executing at optimal rates.
A second approach to maximizing the performance of a computer system was to minimize the number of times a processor unit was required to access the system memory in order to obtain data stored therein. This approach contemplated the use of a very high speed memory limited capacity called a cache memory. The most recent information requested by the central processor unit from the system's memory would be stored in the cache memory simultaneously with its transfer to the processor unit. Subsequent requests for such information would result in the transfer of the data directly from the cache to the processing unit without any need for accessing the large capacity but slower system memory.
A third approach to increasing the performance of a data processing system was in fact a hybrid of the first and second approaches and contemplated providing multiple specialized processors within the data processor system and employing the cache memory for the controlling processor, e.g., the CPU. This ameliorated to a degree the lack of capacity to transfer sufficient data to the processors to enable them to operate efficiently. The CPU was, however, primarily benefitted because it was directly connected to the cache memory and it was required to access the system memory less often. A secondary benefit was provided to the other processors because a decrease in traffic on the data bus transferring information between the system memory and the processors resulted from the fewer requests for access by the CPU.
Even the hybrid approach, however, has not resulted in a data processing system wherein multiple specialized processors can be continually optimally operated. A significant impediment to maximizing the processor capabilities of the data processing system still arises from the inability to transfer information within the system at sufficiently high rates in order to take advantage of the inherent efficiencies of multiple, specially designed processors.
Another limitation to the performance of the system is the size of the operand that the CPU can process during a single machine cycle. CPU's such as described in U.S. Pat. No. 4,206,503 are limited to a 16-bit word.